Chemical mechanical polishing (CMP) is a technique that has been conventionally used for planarization of semiconductor wafers. It is often used in the formation of microelectronic devices to provide a substantially smooth, planar surface suitable for subsequent fabrication processes such as photoresist coating and pattern definition. A typical CMP apparatus 10 suitable for planarizing a semiconductor surface is illustrated in FIG. 1 and includes a wafer carrier 12 configured to support, guide, and apply pressure to a wafer 14 during the polishing process. The carrier 12 may be raised and lowered to load a wafer, and may be rotated about a first axis 16. The carrier may comprise a pressure control system 24 that applies a substantially constant pressure distributed across the back of the wafer 14. The pressure control system may take any suitable form, such as, for example, that of an inflated bladder formed from an elastomeric material. A retaining ring 18 may be provided to prevent the wafer 14 from being dragged out from between the carrier 12 and a polishing pad 20 by polishing forces. The polishing pad 20 is supported by a rigid platen 22 that may rotate about a second axis 26 or, alternatively, may move in an orbital, linear or other motion. The polishing pad typically comprises a polymeric material with a predetermined elastic modulus and surface structure that simultaneously provide effective polishing of the wafer and compliance with the wafer over lateral features that may differ in height on the order of several centimeters. Motion is imparted to the wafer carrier 12 and to the polishing pad 20 so that the wafer is rubbed against the pad. A liquid slurry 28 may be injected onto the pad via a nozzle 30 or may be distributed to the polishing pad surface through the polishing pad to chemically weaken the molecular bonds at the wafer surface so that the mechanical action of the polishing pad and slurry can remove the undesired material from the wafer surface.
However, conventional CMP processes tend to leave stresses in the worked wafer leading to subsequent cracking and shorting between metal layers of the wafer. Furthermore, conventional CMP processes may result in sheering or crushing of fragile dielectric layers. These processes also have a tendency to cause dishing in the center of wide metal features, such as trenches and vias, oxide erosion between metal features, and dielectric oxide loss. Electrochemical mechanical planarization (ECMP) is an attractive alternative to removal of metal by CMP because it does not impart significant mechanical stresses to the wafer, and consequently does not significantly reduce the integrity of the devices. In addition, because the removal rate of the metal may be completely controlled by a current flowing through the metal, ECMP is less likely to cause dishing, oxide erosion, and oxide loss of the dielectric layer.
In ECMP, metal removal is accomplished by electrolysis rather than by the corrosive action of a slurry. A conventional ECMP system, illustrated in FIG. 2, is similar to a CMP system in that it comprises a wafer carrier 12 that carries a wafer 14 and comprises a polishing pad 20 that is supported by a rigid platen 22. Electric contacts 42 (anodes) may be disposed within the platen 22 and extend through the polishing pad 20 to make contact with the surface of the wafer 14. To complete the ECMP system 40, the wafer is exposed to an electric field in the presence of an electrolyte 48. In this regard, counterelectrodes 44 are provided. Varying voltages may be imposed between the wafer and the counterelectrodes by a power supply 46. The counterelectrodes 44 allow for a degree of “tuning” of the uniformity of removal of the metal by passing varying current through the individual electrodes. The pad typically comprises holes to allow ion transport from the wafer 14 to the counterelectrodes 44 or, alternatively, the pad is sufficiently porous that this ion transfer may occur. The electrolyte 48 may be dispensed onto the polishing pad or may be distributed through the polishing pad to the wafer surface.
However, conventional ECMP systems have certain drawbacks. With the use of conventional high resistivity electrolytes, a region of a wafer with a high density of metal will experience a larger current density (averaged over a region of lateral dimension of hundreds of microns) than a region of the wafer with a lower density of metal. This variation in current density leads to variations in the voltage distribution in the electrolyte and to a redistribution of the electric field. This leads to a higher removal rate over regions of high metal density than over regions of smaller metal density. This effect can be minimized by reducing the spacing between the wafer and the counterelectrode. However, in typical ECMP systems, the counterelectrode generally is no closer to the wafer than the thickness of the polishing pad.
In addition, during an ECMP process, the metal removed from the wafer may be deposited on the counterelectrodes. This deposited metal may change the spacing between the wafer and the counterelectrode and may be a source of unwanted particulates due to poor adhesion of the metal deposit. While it may be desirable to fabricate the counterelectrode from a noble metal such as platinum, palladium, or gold, these materials are costly and thus fabricating solid counterelectrodes from such metals is impractical. Platinum group metals also tend to absorb hydrogen when used as cathodes, which may result in long term drifts in the behavior of such electrodes. In addition, wear of the cathodes during ECMP processes requires replacement of the cathodes at periodic intervals.
Accordingly, it is desirable to provide a conductive polishing assembly for use in ECMP processing that overcomes these drawbacks. In addition, it is desirable to provide a conductive polishing assembly that provides controlled planarization of the wafer surface. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.